1. Field of the Invention
The present invention relates to a method of manufacturing a non-volatile memory. More particularly, the present invention relates to a method of manufacturing a split-gate flash memory having a cell region and peripheral circuit regions.
A claim of priority is made to Korean Patent Application No. 2003-84733 filed on Nov. 26, 2003, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
A non-volatile memory maintains data stored in its constituent memory cells even in those circumstances where power is not applied to the memory. Examples of non-volatile memory types include; mask ROMs, erasable and programmable ROMs (EPROMs), and an electrically erasable and programmable ROM (EEPROMs). Flash memory is one form of EEPROM in which one transistor constitutes one memory cell.
Different flash memory types include the stacked gate flash memory and the split-gate flash memory. As the names suggest, these flash memory types are differentiated according to their corresponding cell transistor gate structure. A stacked gate flash memory includes a floating gate for storing charge, and a control gate for controlling operation of the device. As physically implemented, these two gate structures are stacked one over the other.
A split-gate flash memory also includes a floating gate and a control gate. However, in the split-gate flash memory, the control gate is physically implemented next to (or laterally adjacent to) the floating gate. Conventional split-gate flash memories are characterized by excellent efficiency in their erasure/program functionality. This high efficiency effectively protects split-gate memories from inadvertent over-erasure of stored data. As a result, split-gate flash memories are widely used. An example of one conventional split-gate flash memory device is disclosed in U.S. Pat. No. 6,524,915.
FIGS. 1 to 9 are cross-sectional views illustrating a conventional method adapted to the manufacture of a split-gate flash memory.
Referring to FIG. 1, a coupling insulating film 2, a floating gate conductive film 3 formed from a conductive polycrystalline silicon, and a mold film 4 formed from a nitride film are collectively formed on a substrate 1. The substrate can readily be divided into a cell region “a” and peripheral circuit regions “b” and “c”. A trench 5 is formed by patterning the mold film 4, such that a predetermined portion of the floating gate conductive film 3 is exposed within in cell region “a”. A thermal oxide film 27 is formed by thermal oxidation of the floating gate conductive film 3 portion exposed by trench 5. Alternatively, an end portion of the floating gate, on which an electric field is concentrated when the completed memory device is erased, is formed by recessing a portion of the floating gate conductive film 3 exposed by trench 5 by a predetermined thickness before performing a thermal oxidation process to form thermal oxide film 27.
Preliminary spacers 6 formed from a silicon oxide film are formed on both sides of trench 5. Preliminary spacers 6 and the mold film 4 are used as etching masks to etch the floating gate conductive film 3 and the coupling insulating film 2 to expose a region of semiconductor substrate 1. Ions are implanted into the exposed region on the semiconductor substrate 1 to form a source junction region 7. A liner oxide film (not shown) is then formed on the entire surface of the substrate 1 and etched to form liner spacers 8 on the sides of preliminary spacers 6 and the exposed sidewalls of floating gate 3. Liner spacers 8 and preliminary spacers 6 may be collectively grouped together as individual spacers 9. A source conductive film 10 formed from a conductive polycrystalline silicon is formed on the entire surface of semiconductor substrate 1, such that trench 5 is filled with the source conductive film 10.
Referring to FIG. 2, Chemical Mechanical Polishing (CMP) is performed on the source conductive film 10 until a portion of mold film 4 is exposed (not shown), thereby forming a source line 10a in trench 5. An upper portion of source line 10a is thermally oxidized to form a mask film 10b. The residual exposed portion of mold film 4, most of floating gate conductive film 3 and coupling insulating film 2 are sequentially etched to expose portions of semiconductor substrate 1 in the cell region “a” extending beyond the cell structure shown in FIG. 2. Portions of semiconductor substrate 1 in the peripheral circuit regions “b” and “c” are similarly exposed.
Referring now to FIG. 3, an oxide film 11 is formed on the entire surface of the exposed semiconductor substrate 1 to form a control gate insulating film and a high voltage gate insulating film.
Referring to FIG. 4, the portion of oxide film 11 covering low voltage region “c” of the semiconductor substrate is removed by dry etching with the use of a photoresist pattern 50.
Referring to FIG. 5, an oxide film 12 is thereafter formed on the surface of the low voltage region “c” of the semiconductor substrate to form a low voltage gate insulating film 12. In the process of forming low voltage gate insulating film 12, the thickness of portion 11a of the control gate insulating film and the tunneling insulating film on the cell region “a” of the semiconductor substrate, and the thickness of portion 11a of the high voltage gate insulating film on the high voltage region “b” of the semiconductor substrate are both increased by a thickness corresponding to the thickness of low voltage gate insulating film 12.
Referring to FIG. 6, a control gate conductive film 22 formed from a conductive polycrystalline silicon film and an oxidation prevention film 23 formed from a silicon nitride are formed on the control gate insulating film/high voltage gate insulating film 11a and low voltage gate insulating film 12.
Referring to FIG. 7, CMP is performed on the oxidation prevention film 23 and the control gate conductive film 22 until the upper surface of the source line 10a is exposed. Accordingly, the oxidation prevention film pattern 23a is largely removed from cell region “a”, and upper surface portions of the control gate conductive 22 are exposed between each spacer 9 and the oxidation prevention film pattern 23a. In peripheral circuit regions “b” and “c”, an oxidation prevention film pattern 23a is formed during the same processing step(s) used to form the oxidation prevention film pattern 23a found in cell region “a”. Thus, upper surface portions of the exposed control gate conductive film 22 in cell region “a” and an upper surface of source line 10a are thermally oxidized to form a hard mask film 25.
Referring now to FIG. 8, the oxidation prevention film 23a is etched away using the hard mask film 25 as an etching mask to expose the control gate conductive film 22. A photoresist film is formed in peripheral circuit regions “b” and “c” to pattern a transistor gate.
Referring to FIG. 9, control gate conductive film 22 is etched using hard mask film 25 and photoresist pattern 60 as etching masks to form a control gate line 22a in cell region “a”, a high voltage transistor gate 22b in the high voltage region “b”, and a low voltage transistor gate 22c in the low voltage region “c”. After nitride spacers are formed on the sidewalls of control gate line 22a, a portion of the semiconductor substrate 1 on which a drain junction region will be formed is exposed. Ions are implanted in semiconductor substrate 1 to form a drain junction region (not shown). Numerical reference 11a denotes an insulating film formed by a deposition process, which serves as a tunneling insulating film at a tip portion 30 of the floating gate 3a, and which serves as a control gate insulating film under control gate 22a and high voltage gate insulating film on high voltage region “b”.
Staying with FIG. 9, an erase and program operation(s) for the conventional split-gate flash memory will be described. In the program operation, a high voltage VDD is applied to a source junction region through source line 10a. A low voltage (e.g., between 0 and 1.0 Volts) is applied to a drain junction region. Under these voltage conditions, electrons generated in the drain junction region move towards the source junction region through a channel region inverted slightly by a threshold voltage Vth applied to the control gate 22a. The electrons moving toward the source junction region are excited by the potential difference between the drain junction region and the floating gate 3a which is coupled to high voltage VDD applied via source line 10a. In this manner, electrons are injected into the floating gate 3a. In other words, the program operation is performed by hot carrier injection into the floating gate 3a. 
In an erase operation, high voltage VDD is applied to control gate 22a and a low voltage is applied to the source and drain junction regions. The electrons accumulated in floating gate 3a leaked out from the tapered tip of floating gate 3a to control gate 22a through tunneling insulating film 11a by means of a conventionally understood tunneling (Fowler-Nordheim) phenomenon. Accordingly, the threshold voltage Vth for the channel is shifted to a lower value, and the corresponding cell enters into an erasing state.
Referring still to FIG. 9, since the tunneling insulating film 11a is adjacent to the tip 30 of floating gate 3a and has the same thickness as the high voltage gate insulating film 11a near high voltage transistor gate 22b, overall erasing efficiency for the split-gate flash memory device is relatively low. That is, in order to apply sufficient voltage to control gate 22a, high voltage gate insulating film 11a must be relatively thick. In contrast, if tunneling insulating film 11a has the same thickness as the high voltage gate insulating film 11a, electron tunneling remains relatively inactive. As a result, the erasure operation properties of the flash memory device degrade accordingly.